This invention relates to a microprocessor with an internal data memory, some or all of the data of which are initially set.
FIG. 1 is a block diagram showing one example of a microprocessor. In FIG. 1, reference numeral 1 designates an arithmetic circuit; 2, an accumulator unit; 3, a general purpose register unit; 4, a control circuit; 5, a read-only memory (ROM); 6, an internal data memory; and 7, a power source for driving the internal data memory.
Where the microprocessor thus organized carries out a control or arithmetic operation with the arithmetic circuit 1, the accumulator unit 2, the general purpose register unit 3 and the control circuit 4, the data to be computed or source operands are stored in the internal data memory 6, and the results of the execution of the control or arithmetic operation are generally stored in the internal data memory 6.
The internal data memory in the micro-processor is, in general, made up of a plurality of memory cells which are ramdom access memories.
FIG. 2 is a circuit diagram of a memory cell. In FIG. 2, reference character Tr.sub.1 designates an enhancement type driver transistor, and Tr.sub.3, a depletion type load transistor which is connected in series with the driver transistor Tr.sub.1. The load transistor Tr.sub.3 and the driver transistor Tr.sub.1 form a first inverter circuit. The source of the driver transistor Tr.sub.1 is connected to a ground line GL, the drain of the load transistor Tr.sub.3 is connected to a power source line VL, and the gate of the load transistor is connected to the connecting point of its source and the drain of the driver transistor Tr.sub.1.
Reference character Tr.sub.2 designates an enhancement type driver transistor, and Tr.sub.4, a depletion type load transistor which is connected in series with the driver transistor Tr.sub.2. These transistors Tr.sub.2 and Tr.sub.4 form a second inverter circuit. The source of the driver transistor Tr.sub.2 is connected to the ground line GL, the drain of the load transistor Tr.sub.4 is connected to the power source line VL, and the gate of the load transistor Tr.sub.4 is connected to the connecting point of its source and the drain of the driver transistor Tr.sub.2. The gate of the driver transistor Tr.sub.1 in the first inverter circuit is connected to the drain of the driver transistor Tr.sub.2 in the second inverter circuit, while the gate of the driver transistor in the second inverter circuit is connected to the drain of the driver transistor Tr.sub.1 in the first inverter circuit. That is, the first and second inverters including the transistors Tr.sub.1 through Tr.sub.4 form a feedback type flip-flop circuit to store data. Further in FIG. 2, reference characters Tr.sub.5 and Tr.sub.6 designate writing and reading transfer gate elements. The transfer gate element Tr.sub.5 is connected between the drain of the driver transistor Tr.sub.1 and a first bit line BL.sub.1, and its gate is connected to a word line WL. The transfer gate element Tr.sub.6 is connected between the drain of the driver transistor Tr.sub.2 and a second bit line BL.sub.2, and its gate is connected to the word line WL.
In the memory cell thus organized, ordinary operation is as follows: When a signal is written in the cell through the transfer gate Tr.sub.5, the signal is applied to the gate of the driver transistor Tr.sub.2. Therefore, the signal, after being amplified and inverted by the second inverter circuit comprising the driver transistor Tr.sub.2 and the load transistor Tr.sub.4, appears at the drain of the driver transistor Tr.sub.2 and is applied to the gate of the driver transistor Tr.sub.1. The signal thus processed is amplified and inverted by the first inverter circuit and appears at the drain of the driver transistor Tr.sub.1 which is the input point; that is, the data is self-held. In the reading operation, a voltage is applied to the gates of the transfer gate elements Tr.sub.5 and Tr.sub.6 through the word line, so that the drain voltages of the driver transistors Tr.sub.1 and Tr.sub.2 are subjected to comparison.
Heretofore, the memory cell shown in FIG. 2 has had a layout pattern as shown in FIG. 3. In FIG. 3, reference character 8a designates an n.sup.+ diffusion region which is connected to the first bit line BL.sub.1 at one end; 8b, an n.sup.+ diffusion region connected to the second bit line BL.sub.2 at one end; 8c, an n.sup.+ diffusion region which is substantially in the form of a reversed "S", the region 8c being connected to the n.sup.+ diffusion region 8b at one end. Further in FIG. 3, reference character 9a designates a polycrystalline silicon region which is laid over the n.sup.+ diffusion region 8a and 8c to form the depletion type load transistor Tr.sub.3 and the driver transistor Tr.sub.2, respectively; reference character 9b designates a polycrystalline silicon region laid over the n.sup.+ diffusion regions 8b and 8c to form the depletion type load transistor Tr.sub.4 and the driver transistor Tr.sub.1, respectively; and reference character 9c designates a polycrystalline silicon region connected to the word line WL and which is laid over the n.sup.+ diffusion regions 8a and 8b to form the transfer gate elements Tr.sub.5 and Tr.sub.6, respectively. Further in FIG. 3, reference characters 10a through 10c designate contact holes which connect the n.sup.+ diffusion regions 8a through 8c to the polycrystalline silicon regions 9a and 9b as illustrated; 11a, an aluminum wiring line connected to the power source line VL and connected to the n.sup.+ diffusion regions 8a and 8b respectively through contact holes 12a and 12b; and 11b, an aluminum wiring line which is connected to the ground line GL and is connected through a contact hole 12c to the middle point between the driver transistors Tr.sub.1 and Tr.sub.2 formed by the n.sup.+ diffusion region 8c.
In the memory cell having the above-described lay-out pattern, for stable writing and reading operations the sizes (channel length and channel width) of the transistors are in a certain ratio, and the first and second inverter circuits are symmetrical with each other, i.e., they are designed so as to be equal in transistor size parameters, thus having equivalent "on" levels.
Accordingly, when the power source is connected to the memory cell, its bit logic is set to "1" to "0". However, the memory cell is unstable, because the transistors in the pair of inverter circuits are equally arranged and there is no element which can determine which of the logic values should be selected. Furthermore, the drain voltages of the driver transistors Tr.sub.1 and Tr.sub.2, i.e., the held data, are affected because of fluctuations in the transistor sizes and in the threshold voltages of the transistors Tr.sub.1 through Tr.sub.4, and fluctuation in the values of resistors and capacitors provided together with the memory cell, when the power switch is turned on. Accordingly, in the microprocessor having the internal data memory 6 using the memory cells shown in FIG. 3, the data in the internal data memory 6 is unstable when the power switch is turned on. Therefore, when control and operation functions are carried out with the arithmetic circuit 1, the accumulator unit 2, the general purpose register unit 3 and the control circuit 4, and in the case where the data stored in the internal data memory 6 are used as the source operands, it is necessary that data be written in the internal data memory by means of software such as a monitor program in advance, for initial setting. This is undesirable from the viewpoint of the effective use of software. Furthermore, the initial setting program, which is required only when the power switch is turned on, requires a program memory region like an ordinary program.